Binary counters are fundamental components of microprocessors, memory circuits, digital signal processors, communications hardware and numerous other electronic devices. The ever-increasing demand for higher speed and bandwidth in such devices requires that counters operate faster and support a longer word length. A binary counter typically includes a number of interconnected flip-flops or other single-bit storage elements. The flip-flops are arranged to provide a number of parallel outputs each representing a bit of a binary number indicative of a count of clock cycles since a previous reset. The counter may be configured to increment or decrement a count by one with each clock cycle. In a type of binary counter known as a synchronous binary counter, a common clock signal is used to clock each of the flip-flops in the counter. Such an arrangement limits the maximum clock rate of the counter in that the clock period generally must be greater than the time required for a carry to propagate from an initial stage of the counter corresponding to the least significant bit (LSB) of the count to a final stage corresponding to the most significant bit (MSB). In a ripple-carry counter, a carry generated by an earlier counter stage is supplied to the next counter stage before the next stage can generate a carry. The carry propagation delay is therefore proportional to the number of stages in the counter.
FIG. 1 shows a portion of a conventional binary synchronous ripple-carry counter 10. The counter 10 is an N-bit counter divided into K stages each storing N/K bits. FIG. 1 includes a detailed view of a single exemplary stage 12.sub.i of the N-bit counter with K stages, where N/K=4, and also illustrates interconnection of stage 12.sub.i with a previous stage 12.sub.i-1 and a subsequent stage 12.sub.i+1 of the counter 10. The stage 12.sub.i receives a carry-in signal C.sub.IN from the previous stage, 12.sub.i-1, and delivers a carry-out signal C.sub.OUT to the subsequent stage 12.sub.i+1. The stage 12.sub.i includes four D-type flip-flops 14-0, 14-1, 14-2 and 14-3 arranged as shown. The uncomplemented outputs of the flip-flops 14-0, 14-1, 14-2 and 14-3 provide the Q.sub.0, Q.sub.1, Q.sub.2 and Q.sub.3 outputs, respectively, of counter stage 12.sub.i. Each of the flip-flops 14-0, 14-1, 14-2 and 14-3 is clocked by a common clock signal CLK. The d.sub.0, d.sub.1, d.sub.2 and d.sub.3 data inputs of the respective flip-flops 14-0, 14-1, 14-2 and 14-3 are driven by the outputs of corresponding respective two-input exclusive-or (XOR) gates 16-0, 16-1, 16-2 and 16-3. One of the inputs of each of the XOR gates is driven by the output of one of the flip-flops as shown. The carry-in signal C.sub.IN from previous gate 12.sub.i-1 is coupled to the other input of XOR gate 16-0 and to an input of AND gate 18-1. The remaining XOR gates 16-1, 16-2 and 16-3 each have their other input driven by the one of the outputs c.sub.1, c.sub.2 and c.sub.3 of AND gates 18-1, 18-2 and 18-3, respectively, as shown. The c.sub.3 output of AND gate 18-3 is connected to one input of an AND gate 20 which generates the carry-out signal C.sub.OUT. The other input of AND gate 20 is connected to the Q.sub.3 output of flip-flop 14-3.
The carry-in signal C.sub.IN received from counter stage 12.sub.i-1 is delayed with respect to the clock signal CLK due to gate delays in stage 12.sub.i-1 and other stages before it. If C.sub.IN is assumed to arrive in stage 12.sub.i at time t.sub.cin, the critical path delay t.sub.Qcrit for latching Q.sub.3 in stage 12.sub.i may be written as: EQU t.sub.Qcrit =t.sub.cin +3.multidot.t.sub.and2 +t.sub.xor2 +t.sub.lset( 1)
where t.sub.and2 is the delay of a two-input AND gate, t.sub.xor2 is the delay of a two-input XOR gate, and t.sub.lset is the latch settling delay of the D-type flip-flops. Similarly, the delay t.sub.Ccrit for the carry-out signal C.sub.OUT can be given by: EQU t.sub.Ccrit =t.sub.cin +4.multidot.t.sub.and2 ( 2)
Equations (1) and (2) above can be generalized to express the critical path delay of a given ripple-carry counter stage 12.sub.i of N/K bits, as follows: ##EQU1## Using Equations (3) and (4), the total critical path delay T.sub.crit for an N-bit synchronous ripple-carry counter, with K stages of N/K bits each, may be written as: EQU T.sub.crit =(K-2).multidot.t.sub.Ccrit +t.sub.Qcrit +t.sub.0crit( 5)
where t.sub.0crit is the carry-out delay of the first counter stage. Since the first counter stage does not have any carry coming in, t.sub.0crit is simply the delay of ((N/K)-1) two-input AND gates: ##EQU2## Using Equations (3), (4), (5) and (6), the critical path delay T.sub.crit may be written as: ##EQU3##
A number of techniques are available for reducing the critical path delay T.sub.crit through use of fast addition circuits. One such technique reduces the delay attributable to the first term of Equation (7) by using (N/K)-input AND gates in parallel with (K-2) two-input AND gates. The critical path delay in this case becomes: ##EQU4## where t.sub.andN/K is the delay of the (N/K)-input AND gate. Although such techniques do provide some reduction in the critical path delay of a ripple-carry counter, the delay remains unacceptably high for many important high-speed electronic device applications.
It is therefore apparent that a need exists for a synchronous binary counter which provides a substantially lower critical path delay relative to that provided using conventional techniques, without substantially increasing the cost and complexity of the counter circuit.